An ongoing trend in integrated circuits (ICs) is the attempt to reduce the footprint of the IC. This is addressed, for example, by introducing new processes that allow the gate length to be reduced and thereby allow more transistors to be formed on an IC.
Another recent solution is to provide more than one die on a packaged chip, wherein the die are stacked on top of each other and separated by an insulating material. A typical stacked die is shown in FIG. 1, which shows a bottom dice 100 secured by means of silver epoxy 102 (such as Ablestik 8340) to a die paddle 104. A second, or top, dice 106 is secured to the bottom dice 100 by means of an adhesive layer 108 which can be a Teflon based epoxy such as Loctite Qmi 500. The entire structure, comprising the paddle 104, bottom die 100 and top die 106 are encased in a packaging material, typically referred to as a package (not shown in FIG. 1) and commonly made of a plastics material. In order to provide electrical contact to the two die 100, 106, each die is provided with contacts along its periphery, and bonding wires (not shown) are connected to the contacts by means of gold ball bonds 110. As shown in FIG. 1, in order to avoid the top die 106 from interfering with the gold ball bonds 110 of the bottom die 100, the top die 106, in this embodiment, is smaller than the bottom die 100. However, it should be noted that this configuration is shown for illustration purposes only. More than two die can be stacked on top of each other and at the time of this application, stacking four die on top of each other is known in the art. Also, it is not necessary that the die be smaller toward the top of the stack. The epoxy layers and spacers between the die can sufficiently space the die to accommodate the gold ball bonds.
A problem facing the industry is in the testing of such stacked die devices after they have been stacked and packaged. It is common for faulty die to be returned by customers (e.g. original equipment manufacturers (OEMs)) to the manufacturer for analysis to determine the cause of the fault. In the case of non-stacked die this involves the decapping of the IC, i.e. the top of the package is removed by mechanical grinding or chemical etching. With the IC exposed, electrical testing contacts (other than the I/O contacts on the periphery of the IC become accessible for attaching needles of testing equipment or otherwise testing the IC. However, in the case of a stacked device, there is more than one die. Thus, at least some of the electrical contacts and circuitry of the bottom die are typically covered by the top die, and cannot be accessed. Furthermore, it may not always be possible to isolate the characteristics of individual devices since the functioning of devices on one die is impacted by the devices on the other die, since the die are interconnected to allow all of the die to work as one large IC. This interconnection may take place externally (on the printed circuit board on which the stacked device is mounted), or by die-to-die gold wire bonds, or internally by having vias through the epoxy between the die, to thereby allow electrical connection between contacts on one die and contacts of another die.
The present invention seeks to provide a way of testing stacked ICs and also seeks to provide a process for forming stacked ICs that makes the ICs more amenable to subsequent testing.